← 返回 JSSC 论文列表JSSC 2009第5期Clocking & PLLs0.13μmNeural Network Accelerator
A Low Jitter Programmable Clock Multiplier Based on a Pulse Injection-Locked Oscillator With a Highly-Digital Tuning Loop Belal M. Helal , Member , IEEE
基于脉冲注入锁定振荡器的低抖动可编程时钟倍频器
0.13μm, 0.4mm², 28.6mW, 3.2GHz, 130fs (rms), 63.9dBc, 200fs (peak-to-peak)
低抖动时钟倍频脉冲注入锁定数字反馈相位噪声
▸创新点1：脉冲注入锁定振荡器（PILO）设计，通过脉冲注入技术实现低抖动时钟倍频，显著提升输出时钟信号的相位噪声性能。
▸创新点2：数字反馈电路连续调谐，采用全数字反馈机制实时调整振荡器频率，确保其自然频率与注入频率精确锁定，提高系统稳定性。
▸创新点3：低抖动时钟倍频，通过优化电路设计和反馈控制，实现从50 MHz到3.2 GHz的高精度倍频，抖动低至130 fs (rms)。
▸创新点4：系统集成创新，结合FPGA、离散DAC和简单RC滤波器，构建高效的原型系统，验证了PILO在实际应用中的可行性。
Abstract
This paper introduces a pulse injection-locked oscil- lator (PILO) that provides low jitter clock multiplication of a clean input reference clock. A mostly-digital feedback circuit provides continuous tuning of the oscillator such that its natural frequency is locked to the injected frequency. The proposed system is demon- strated with a prototype consisting of a custom 0.13 m integrated circuit with active area of 0.4 mm /50and core power of 28.6 mW, along with an FPGA, a discrete DAC and a simple RC filter. Using a low jitter 50 MHz reference input, the PILO prototype generates a 3.2 GHz output with integrated phase noise, reference spur , and estimated deterministic jitter of 130 fs (rms), 63.9 dBc, and 200 fs (peak-to-peak), respectively.