← 返回 JSSC 论文列表JSSC 2009第5期RF & Wireless90nmTransceiver
A Phase Domain Approach for Mitigation of Self-Interference in Wireless Transcei
提出一种相位域方法，用于抑制无线收发器中的自干扰，应用于GSM收发器的PLL参考时钟抖动最小化。
90nm CMOS
自干扰抑制无线收发器相位域PLLGSM
▸创新点1：相位调整技术利用数字密集型PLL特性，通过数字信号处理资源实现精确相位调整，有效减少参考时钟抖动，提升系统稳定性。
▸创新点2：无需额外硬件，不增加功耗，通过优化现有数字密集型PLL架构，实现低成本的自干扰抑制解决方案。
▸创新点3：识别并解决复杂干扰机制，详细分析多RF干扰源对参考时钟的影响，提出针对性的相位调整策略，显著降低带内相位噪声。
▸创新点4：基于90nm CMOS工艺的DRP技术实现，验证了该相位调整技术在GSM SoC中的实际应用效果，展示了其在高度集成无线收发器中的广泛适用性。
Abstract
gdan Staszewski , Fellow, IEEE ,
Imran Bashir, Associate Member , IEEE, Sumeer Bhatara , Member , IEEE, and Poras T. Balsara , Senior Member , IEEE
Abstract—A novel approach for mitigation of self-interference
in highly-integrated wireless transceivers is presented. Several ex-
amples of possible applications of this approach in a wireless cel-
lular transceiver system-on-chip (SoC) are listed, and the applica-
tion of one example is presented in detail. Mathematical analysis,
simulation results