JSSC 2009第5期Data Converters90nmVCO

Measurements and Analysis of Process Variability in 90 nm CMOS Liang-Teck Pang M

研究90纳米CMOS工艺中电路布局对变异性的影响及延迟和漏电流的WID与D2D变异性

90nm CMOS, 延迟变异3.5%, D2D变异15%, 布局诱导频率偏移10%

CMOS工艺变异性多晶硅栅环形振荡器漏电流

▸分析多晶硅栅密度对晶体管性能的影响

▸研究空间相关性与栅极取向及间距方向的关系

▸提出减轻工艺变异影响的电路设计指南

Abstract

, IEEE Abstract—A test chip has been built to study the effects of cir- cuit layout on variability, and to characterize within-die (WID) and die-to-die (D2D) variability of delay and leakage current in 90 nm CMOS technology. Delay is obtained through the measurement of ring oscillator frequencies, and the transistor leakage current is measured by an on-chip analog-to-digital converter (ADC). It has been found that the transistor performance depends strongly on the polysilicon (poly-Si) gate dens