A 35-GS/s, 4-Bit Flash ADC With Active Data and Clock Distribution Trees Shahriar Shahramian, Student Member , IEEE, Sorin P . V oinigescu, Senior Member , IEEE, and Anthony

Abstract

This paper presents a 35-GS/s, 4-bit flash ADC-DAC with active data and clock distribution trees. At mm-wave clock frequencies, skew due to mismatch in the clock and data distribu- tion paths is a significant challenge for both flash and time-inter- leaved converter architectures. A full-rate front-end track and hold amplifier (THA) may be used to reduce the effect of skew. How- ever, it is found that the THA output must then be distributed to the comparators with a bandwidth greater than the sampling fre- quency in order to preserve the flat regions of the track and hold waveform. Instead, if the data and clock distribution have very low skew, the THA can be omitted thus obviating the associated non- linearities and resulting in improved performance. In this work, a tree of fully symmetric and linear BiCMOS buffers, called a “data tree”, distributes the input to the comparator bank with a mea- sured 3-dB bandwidth of 16 GHz. The data tree is integrated into a complete 4-bit ADC including a full-rate input THA that can be disabled and a 4-bit thermometer-code DAC for testing purposes. The chip occupies 2.5 mm 3.2 mm including pads and is imple- mented in 0.18 m SiGe BiCMOS technology. The ADC consumes 4.5 W from a 3.3 V supply while the DAC operates from a 5 V supply and consumes 0.5 W. The ADC has 3.7 ENOB with a 3-dB effective resolution bandwidth of 8 GHz and a full-scale differen- tial input range of 0.24 . With the THA enabled, the perfor- mance degrades rapidly beyond 8 GHz