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A V oltage Scalable 026 V 64 kb 8T SRAM With V109105110Lowering Techniques and
本文实现了一种电压可扩展的0.26V 64kb 8T SRAM，采用130nm CMOS工艺，通过多种技术降低功耗并提高性能。
130nm CMOS, 0.26V, 64kb
位线泄漏补偿浮动位线低电压SRAM设计最小工作电压睡眠模式
▸利用反向短沟道效应提升SRAM写入裕度和读取性能
▸边际位线泄漏补偿方案降低亚阈值电压下的泄漏电流
▸浮动位线方案减少泄漏功耗
Abstract
, IEEE, Jason Liu , Member , IEEE, and Chris H. Kim , Member , IEEE
Abstract—A voltage scalable 0.26 V , 64 kb 8T SRAM with 512
cells per bitline is implemented in a 130 nm CMOS process. Uti-
lization of the reverse short channel effect in a SRAM cell design
improves cell write margin and read performance without the aid
of peripheral circuits. A marginal bitline leakage compensation
(MBLC) scheme compensates for the bitline leakage current which
becomes comparable to a read current at subthres