← 返回 JSSC 论文列表JSSC 2009第6期RF & Wireless0.25μm CMOS, 90nm CMOSDelta-Sigma ADC
Comments and Corrections Correction to “A 2.7 mW, 90.3 dB DR Continuous-Time Quadrature Bandpass Sigma-Delta Modulator for GSM/EDGE Low-IF Receiver in 0.25 m CMOS” Song-Bok Kim
对两篇IEEE JSSC论文的更正和评论。
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IEEE JSSC更正单比特量化器数字调制极性功率放大器CMOS
▸创新点1：单比特量化器电路优化，通过将PMOS晶体管替换为NMOS，显著提升量化器的响应速度和噪声性能，属于电路级创新。
▸创新点2：数字调制极性CMOS功率放大器架构的文献补充，完善了技术背景和对比分析，增强了论文的学术严谨性，属于方法创新。
▸创新点3：针对GSM/EDGE低中频接收机的连续时间正交带通Sigma-Delta调制器设计，实现了2.7 mW功耗和90.3 dB动态范围的高性能指标，属于系统级创新。
▸创新点4：在90 nm CMOS工艺中实现低功耗数字包络调制器，验证了极性发射机架构的可行性，为后续研究提供了重要参考，属于电路与系统协同创新。
Abstract
E Low-IF Receiver in 0.25
m CMOS”
Song-Bok Kim
I
N the paper by S.-B. Kim et al. [1], unfortunately an error was
made in Fig. 15 (single-bit quantizer). Two PMOS transistors
should be replaced by NMOS /40/77/53/59/77/54/41as indicated in the corrected
figure below.
Fig. 15. Single-bit quantizer (correction).
REFERENCES
[1] S.-B. Kim, S. Joeres, R. Wunderlich, and S. Heinen, “A 2.7 mW, 90.3
dB DR continuous-time quadrature bandpass sigma-delta modulator
for GSM/EDGE low-IF receiver in 0.25 /22m C