← 返回 JSSC 论文列表JSSC 2009第6期Memory0.35μmCMOS Image Sensor
Focal-Plane Algorithmically-Multiplying CMOS Computational Image Sensor Alireza Nilchi, Student Member , IEEE, Joseph Aziz , Student Member , IEEE
一种在焦平面上实现并行卷积计算的CMOS图像传感器
128x128像素阵列，8x8核卷积，0.35μm CMOS
CMOS图像传感器焦平面计算并行卷积离散小波变换视频压缩
▸创新点1：焦平面并行计算（系统创新）：该CMOS图像传感器在焦平面上直接并行计算视频帧的二维卷积，显著提升了计算效率，减少了数据传输延迟，特别适用于实时视频处理应用。
▸创新点2：可编程数字核卷积（方法创新）：支持高达8x8像素的可编程数字核卷积，提供了灵活的图像处理能力，能够适应多种卷积核需求，增强了传感器的通用性和应用范围。
▸创新点3：双存储像素架构（电路创新）：采用双存储器像素设计，能够同时存储两帧视频数据，实现了帧间差分操作，有效减少了数据处理时间，提高了系统的实时性。
▸创新点4：二进制模拟乘法与列并行累加（电路创新）：通过二进制核系数控制的像素输出采样实现二进制模拟乘法，结合跨像素列并行位级累加，显著提高了乘法运算的效率和精度。
Abstract
The CMOS image sensor computes two-dimensional convolution of video frames with a programmable digital kernel of up to 8 8 pixels in parallel directly on the focal plane. Three operations, a temporal difference, a multiplication and an accumu- lation are performed for each pixel readout. A dual-memory pixel stores two video frames. Selective pixel output sampling controlled by binary kernel coefficients implements binary-analog multiplica- tion. Cross-pixel column-parallel bit-level accumulation and frame differencing are implemented by switched-capacitor integrators. Binary-weighted summation and concurrent quantization is per- formed by a bank of column-parallel multiplying analog-to-digital converters (MADCs). A simple digital adder performs row-wise ac- cumulation during ADC readout. A 128 128 active pixel array integrated with a bank of 128 MADCs was fabricated in a 0.35 m standard CMOS technology. The 4.4 mm 2.9 mm prototype is experimentally validated in discrete wavelet transform (DWT) video compression and frame differencing.