JSSC 2009第7期Data Converters0.18μmDelta-Sigma ADC

A 12-bit 3125 MHz Bandwidth 03 MASH Delta-Sigma Modulator

一款12位3.125MHz带宽的MASH Delta-Sigma调制器，采用0.18μm CMOS工艺，峰值SNDR达73.9dB。

12-bit, 3.125MHz带宽, 50MHz时钟, 73.9dB SNDR, 24mW功耗

Delta-Sigma调制器MASH架构CMOSSNDR能量效率

▸创新点1：采用0-3 MASH架构（系统创新），通过多级噪声整形结构实现12-bit精度和73.9 dB峰值SNDR，显著优于单环结构的64.5 dB性能

▸创新点2：动态可重构拓扑设计（系统创新），支持MASH与单环模式切换，在保持3.125MHz带宽下实现22mW至24mW的功耗灵活调节

▸创新点3：优化能量效率（电路创新），采用MASH架构实现0.95 pJ/step的转换能效，较传统反馈结构(2.57 pJ/step)降低63%

▸创新点4：低电压设计（电路创新），在1.8V电源电压下实现50MHz采样率，通过开关电容电路优化降低工艺节点(0.18μm)限制影响

Abstract

We demonstrate a 12-bit 0–3 MASH delta-sigma mod- ulator with a 3.125 MHz bandwidth in a 0.18 m CMOS tech- nology. The modulator has an oversampling ratio of 8 (clock fre- quency of 50 MHz) and achieves a peak SNDR of 73.9 dB (77.2 dB peak SNR) and consumes 24 mW from a 1.8 V supply. For compar- ison purposes, the modulator can be re-conﬁgured as a single-loop topology where a peak SNDR of 64.5 dB (66.3 dB peak SNR) is ob- tained with 22 mW power consumption. The energy required per conversion