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A 3.6 pJ/Access 480 MHz, 128 kb On-Chip SRAM With 850 MHz Boost Mode in 90 nm CMOS With Tunable Sense Amplifiers
90nm CMOS工艺下实现低能耗、高性能128kb SRAM，支持多种频率模式。
90nm CMOS, 480MHz/850MHz, 2.7pJ/access
SRAM低能耗CMOS感测放大器频率模式
▸创新点1：短缓冲本地位线技术（电路创新）- 通过引入短距离缓冲本地位线设计，显著降低了单元读取电流对存储器延迟的影响，实现了单周期32位/字的快速访问，支持480MHz至850MHz的高频操作。
▸创新点2：扩展全局位线架构（系统创新）- 采用延伸的全局位线布局，减少了感测放大器数量至32个，同时优化了信号传输路径，使正常模式能耗降至3.6pJ/access，高频模式为8.4pJ/access。
▸创新点3：选择性电压缩放技术（方法创新）- 动态调整不同功能模块的供电电压，在保证单元稳定性和速度的前提下，将低功耗模式（240MHz）能耗压降至2.7pJ/access的行业领先水平。
▸创新点4：数字可调谐感测放大器与时序电路（电路创新）- 新型数字化可调谐感测放大器配合自适应时序控制，有效补偿工艺波动导致的性能偏差，提升高频（850MHz Boost模式）下的信号完整性。
Abstract
An extremely low energy per operation, single cycle 32 bit/word, 128 kb SRAM is fabricated in 90 nm CMOS. In the 850 MHz boost mode, total energy consumption is 8.4 pJ/access. This reduces to 3.6 pJ/access in the normal 480 MHz mode and bottoms out at a very aggressive 2.7 pJ/access in the 240 MHz low power mode. Several techniques were combined to obtain these performance numbers. Short buffered local bit lines reduce the im- pact of the cell read current on memory delay. Extended global bit- lines are used which improves delay and energy consumption and which reduces the number of sense amplifiers in the memory to 32. Cell stability and speed issues are avoided by applying selective voltage scaling. Novel, digitally tunable sense amplifiers and a tun- able timing circuit cope gracefully with the stochastic variations in the periphery.