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A 70 pJPulse Analog Front-End in 130 nm CMOS for UWB Impulse Radio Receivers
一种用于超宽带脉冲无线电接收机的70 pJ/脉冲模拟前端设计
130nm CMOS, 1.2V, 39.0625Mpps, 50dB增益, 2.3mA电流
超宽带脉冲无线电模拟前端低功耗CMOS
▸模拟域脉冲相关技术降低ADC和数字后端功耗
▸采用窗口化LO代替匹配模板的相关技术
▸利用系统占空比特性优化功耗
Abstract
This paper presents an integrated ultra-low power
analog front-end (AFE) architecture for UWB impulse radio
receivers. The receiver is targeted towards applications like wire-
less sensor networks typically requiring ultra energy-efficient, low
data-rate communication over a relative short range. The pro-
posed receiver implements pulse correlation in the analog domain
to severely relax the power consumption of the ADCs and digital
backend. Furthermore a fully integrated prototype of the analog
f