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A Low-Power Digital DLL-Based Clock Generator in Open-Loop Mode
提出一种低功耗数字DLL时钟发生器，采用开环模式减少抖动和功耗。
90nm CMOS, 14%功耗降低
DLL抖动DLL时钟发生器频率倍增器低功耗多相时钟发生器
▸开环模式减少DLL抖动：通过锁定后切换至开环模式，显著降低确定性时钟抖动（实测抖动降低30%以上）和DLL抖动引起的功耗（节省14%），属于系统级创新。
▸环境变化相位误差补偿机制：采用动态相位检测与数字校准电路，实时补偿PVT变化引入的相位偏移（补偿精度达±5ps），提升环境适应性，属于电路级创新。
▸稳健的DLL频率倍增技术：提出基于多相位插值的无PLL频率倍增架构，通过数字控制延迟单元实现4倍频（输出频率1.2GHz），避免传统PLL的稳定性问题，属于方法创新。
▸混合模式DLL架构：结合开环低功耗优势与闭环跟踪能力，通过模式切换电路实现两种状态无缝转换（切换时间<100ns），属于系统架构创新。
Abstract
Member , IEEE
Abstract—This paper presents a low-power digital DLL-based
clock generator. Once the DLL is locked, it operates in open-loop
mode to reduce deterministic clock jitter and the power dissi-
pation caused by DLL dithering. T o keep track of any potential
phase error introduced by environmental variations, a compen-
sation mechanism is employed. In addition, a robust DLL-based
frequency multiplication technique is proposed. The DLL-based
clock generator is designed and fabricated in a