A Robust High Speed Serial PHY Architecture With Feed-Forward Correction Clock and

Abstract

This paper describes a robust architecture for high speed serial links for embedded SoC applications, implemented to satisfy the 1.5 Gb/s and 3 Gb/s Serial-A TA PHY standards. To meet the primary design requirements of a sub-system that is very tol- erant of device variability and is easy to port to smaller nanometre CMOS technologies, a minimum of precision analog functions are used. All digital functions are implemented in rail-to-rail CMOS with maximum use of synthesized library cells. A single fixed fre- quency low-jitter PLL serves the transmit and receive paths in both modes so that tracking and lock time issues are eliminated. A new oversampling CDR with a simple feed-forward error correction scheme is proposed which relaxes the requirements for the analog front-end as well as for the received signal quality. Measurements show that the error corrector can almost double the tolerance to in- coming jitter and to DC offsets in the analog front-end. The design occupies less than 0.4 mm /50in 90 nm CMOS and consumes 75 mW.