A Robust High Speed Serial PHY Architecture With Feed-Forward Correction Clock a

Abstract

This paper describes a robust architecture for high speed serial links for embedded SoC applications, implemented to satisfy the 1.5 Gb/s and 3 Gb/s Serial-A TA PHY standards. To meet the primary design requirements of a sub-system that is very tol- erant of device variability and is easy to port to smaller nanometre CMOS technologies, a minimum of precision analog functions are used. All digital functions are implemented in rail-to-rail CMOS with maximum use of synthesized library cells. A sing