← 返回 JSSC 论文列表JSSC 2009第8期Data Converters0.18μmDelta-Sigma ADCOp-Amp
74 dB SNDR Multi-Loop Sturdy-MASH Delta-Sigma Modulator Using 35 dB Open-Loop Op
提出新型多环Delta-Sigma调制器，采用35dB开环运放实现74dB SNDR。
0.18μm CMOS, 1.2V, 20MHz采样频率, 3.2mW功耗, 74dB SNDR@OSR=16
模数转换CMOS模拟集成电路Delta-Sigma调制开关电容电路低功耗设计
▸克服传统多环调制器对高直流增益运放的需求
▸采用环路内数字加法替代输出端数字滤波器
▸结合多环结构稳定性与单环调制器低电路要求优势
Abstract
woo Kwon , Student Member , IEEE, and Un-Ku Moon , Fellow, IEEE
Abstract—This paper presents a new multi-loop delta-sigma
modulator which overcomes the necessity of high DC gain opamps
that were needed in previous multi-loop modulators. Enabling the
use of low gain opamps also allows low-voltage operation due to
the reduced number of transistors between the power supply rails.
In addition, all the digital filters are removed from the output
of this modulator to minimize the overall system require