← 返回 JSSC 论文列表JSSC 2009第8期Clocking & PLLs0.13μm CMOSPLL
A Digital Intensive Fractional-N PLL and All-Digital Self-Calibration Schemes Pi
一种数字密集型分数N锁相环，采用数字滤波器和模拟前馈路径，实现高精度频率补偿。
3.6 GHz, 75 dBc分数杂散, 115.6 dBc/Hz @400 kHz, 134.9 dBc/Hz @3 MHz, 40 mA @1.5V
数字密集型PLL分数N锁相环数字滤波器模拟前馈路径DCO增益校准
▸数字滤波器替代模拟滤波器以减少芯片面积和门泄漏
▸数字校准环路增益和DCO增益至100 ppm精度
▸模拟前馈路径对量化误差和DCO非线性不敏感
Abstract
A digital intensive PLL featuring a digital filter in par-
allel with an analog feed-forward path and a digital controlled os-
cillator (DCO) is presented. Digital loop filter replaces analog pas-
sive filter to reduce chip area and associated gate-leakage in ad-
vanced process. It also allows the PLL loop gain and DCO gain to
be digitally calibrated to within 100 ppm within 50
s. Such fine
frequency resolution enables the PLL to accurately compensate for
the loop parameter variation due to process,