JSSC 2009第8期Power Management0.18μmPLLVCO

Low-Power Supply-Regulation Techniques for Ring Oscillators in Phase-Locked Loops Using a Split-Tuned Architecture Abhijith Arakali, Student Member , IEEE

提出一种低功耗电源调节技术，用于PLL中的环形振荡器，提升电源噪声抑制性能。

0.18μm CMOS, 1.8V, 2.2mA, 1.5GHz, 1.9ps rms jitter, 28dB supply-noise sensitivity

环形振荡器电源噪声灵敏度锁相环分频调谐电压调节器

▸采用分频调谐架构，解耦电源噪声抑制与功耗的权衡

▸在低带宽粗调环路中放置调节器，最大化带宽以抑制振荡器相位噪声

▸基于复制的调节器引入低频极点，避免电源噪声抑制性能退化

Abstract

ali, Student Member , IEEE , Srikanth Gondi , Member , IEEE, and Pavan Kumar Hanumolu, Member , IEEE Abstract—A supply-regulated phase-locked loop (PLL) employs a split-tuned architecture to decouple the tradeoff between supply- noise rejection performance and power consumption. By placing the regulator in the low-bandwidth coarse loop, the proposed PLL architecture allows us to maximize its bandwidth to suppress the oscillator phase noise with neither the power supply-noise rejection nor the po