Abstract
ember , IEEE, Costas J. Spanos , Fellow, IEEE, and
Borivoje Nikolic´, Senior Member , IEEE
Abstract—A test-chip in a low-power 45 nm technology, fea-
turing uniaxial strained-Si, has been built to study variability in
CMOS circuits. Systematic layout-induced variation, die-to-die
(D2D), wafer-to-wafer (W2W) and within-die (WID) variability
has been measured over multiple wafers, analyzed and attributed
to likely causes in the manufacturing process. Delay is charac-
terized using an array of ring