← 返回 JSSC 论文列表JSSC 2009第9期Data Converters0.18-μm CMOSTime-Interleaved ADC
A1 0 15-bit 60-MS/s Floating-Point ADC With Digital Gain and
一种具有数字增益和偏移校准功能的15位60-MS/s浮点ADC
15-bit 60-MS/s, 80 dBFS系统噪声, 300 mW功耗
浮点ADC数字校准伪随机噪声抖动斩波技术可变增益放大器
▸采用数字增益和偏移校准技术
▸使用伪随机噪声（PN）抖动和斩波技术
▸实现恒定带宽的开关电容VGA
Abstract
ng Kyung, Wei-Ming Lee, Bang-Sup Song , Fellow, IEEE, and
Bedabrata Pain
Abstract—Floating-point analog-to-digital converter (FADC)
utilizes an up-front variable-gain amplifier (VGA) to enhance its
low-level resolution. Although it is a single-path system, varying
gain by switching circuit elements in and out modulates the
gain and offset as in the multi-path time-interleaved ADC. For
high-speed operation at all gain settings, a constant-bandwidth
switched-capacitor VGA is implemented with variab