← 返回 JSSC 论文列表JSSC 2009第9期Clocking & PLLs0.18μm CMOSPLLVCO
An FIR-Embedded Noise Filtering Method for 16 Fractional-N PLL Clock Generators
提出一种用于16分数N分频PLL时钟发生器的FIR嵌入式噪声滤波方法，有效抑制带外量化噪声并改善短期抖动性能。
1-GHz ΔΣ分数N分频PLL, 短期抖动降低30%
FIR滤波分数N分频PLL量化噪声时钟发生器短期抖动
▸采用半数字方法的混合FIR滤波技术
▸低OSR ΔΣ调制结合量化噪声抑制
▸对电路失配和非线性具有鲁棒性
Abstract
Sun, Student Member , IEEE, Woogeun Rhee , Member , IEEE, and
Zhihua Wang, Senior Member , IEEE
Abstract—This paper describes a noise filtering method for
/1/6 fractional-
PLL clock generators to reduce out-of-band
phase noise and improve short-term jitter performance. Use of a
low-cost ring VCO mandates a wideband PLL design and com-
plicates filtering out high-frequency quantization noise from the
/1/6 modulator. A hybrid finite impulse response (FIR) filtering
technique based on a semidigital a