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Design and Analysis of A 53-pJ 64-kb Gated Ground SRAM With Multiword ECC
提出一种采用多字ECC和行虚拟地技术的低功耗SRAM架构，显著降低能耗并提升速度。
90nm CMOS, 5.34pJ能耗, 3.3ns数据延迟, 82%每比特能耗节省, 8倍速度提升
错误校正漏电流多字软错误SRAM芯片
▸多字ECC方案（MECC）结合四个数据字形成128位复合ECC字，减少68%校验位
▸行虚拟地技术在保持期间提高地电位至非零值，有效降低漏电功耗
▸提出基于临界电荷的软错误率（SER）模型，验证MECC方案和SER模型的准确性
Abstract
Shah , Student Member , IEEE, David J. Rennie , Member , IEEE,
and Manoj Sachdev , Senior Member , IEEE
Abstract—This paper presents an SRAM architecture em-
ploying a multiword-based ECC (MECC) scheme for soft error
mitigation and a row virtual ground technique for array leakage
reduction. The MECC combines four data words to form a 128
bit composite ECC word, two of which are interleaved in a row
to mitigate cosmic neutron-induced multi-bit errors. The use of
a composite word reduces the numb