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JSSC 2009第9期mm-Wave65nm

Design of Low-Loss Transmission Lines in Scaled CMOS by Accurate Electromagnetic Simulations Federico Vecchi, Student Member , IEEE, Matteo Repossi, Wissam Eyssa

提出一种基于周期性和Floquet定理的精确电磁仿真方法,优化65nm CMOS中的低损耗传输线设计。
0.65 dB/mm @ 60 GHz
传输线CMOS电磁仿真低损耗屏蔽CPW
利用传输线周期性进行精确电磁仿真
有效屏蔽CMOS衬底以降低损耗
实现65nm CMOS中低损耗屏蔽CPW传输线
Abstract
Transmission lines are becoming of common use at mm-wave to implement on-chip functions as impedance matching, filtering and interconnects. Lack of an accurate and fast simula- tion method is nonetheless evident for transmission lines in scaled CMOS where metal dummies inserted for IC planarization make their physical structure extremely complicate. Although lines are not uniform due to displacement of small dummies, they are still periodic. In this paper, we describe an analytical procedure, lever- aging lines periodicity and based on Floquet’s theorem, in order to derive electromagnetic parameters from simulations. Conven- tional, slow-wave and shielded CPWs have been realized in a 65 nm CMOS technology. Thanks to the developed method, an optimum line design has been made possible. The lossy CMOS substrate, responsible for a significant performance degradation, can be ef- fectively shielded and achieved performances are comparable with other technologies considered better suited to implement low-loss, high frequency passive components. Shielded CPW lines show at- tenuation as low as 0.65 dB/mm at 60 GHz, a record in scaled CMOS.