Energy–Performance

Abstract

tract—We propose a new logic family that enables the user to tune the transistor’s effective threshold voltage after fabri- cation for higher speed or lower power. This technique along with dynamic voltage scaling allows simultaneous optimization of static and dynamic power based on the application/workload requirements. Programmable interconnect from an FPGA was implemented using this logic family on a 90 nm CMOS test chip. Measurements show that this topology provides twice the tuning range in