JSSC 2009第10期Other250 nm InP DHBTs/130 nm CMOS

100 GHz Gain-Bandwidth Differential Ampliﬁers in a Wafer Scale Heterogeneously I

采用Si和III-V技术优势的差分放大器，在晶圆级异质集成工艺中实现高性能。

增益带宽积40–130 GHz，低频增益45 dB，6.9 V差分输出摆幅，40 mW功耗

差分放大器异质集成InP DHBTsCMOS增益带宽积

▸晶圆级异质集成工艺：通过将250 nm InP DHBTs与130 nm CMOS在晶圆尺度上异质集成，实现了两种技术的优势互补（高频特性与高集成度），该工艺创新为首次在异构集成工艺中实现高性能IC构建模块的演示。

▸InP DHBTs与130 nm CMOS结合：利用InP DHBTs的高频特性（支持100 GHz增益带宽）和CMOS的低功耗特性（仅40 mW功耗），创造了6.9 V差分输出摆幅和52V/μs超高摆率，属于器件级协同设计创新。

▸新型片上缓冲电路：开发了专用于晶圆级测试的片上缓冲电路，解决了高频放大器在晶圆测试中的信号完整性问题，属于测试方法创新，直接支持40-130 GHz增益带宽产品的表征。

▸性能突破：实现45 dB低频增益与100 GHz级增益带宽乘积，同时兼顾6.9 V高摆幅和52V/μs摆率，在功耗效率（40 mW）方面树立了高频放大器的新标杆，属于系统级性能创新。

Abstract

Differential ampliﬁers incorporating the advantages of both Si and III-V technologies have been fabricated in a wafer scale, heterogeneously integrated, process using both 250 nm InP DHBTs and 130 nm CMOS. These ICs demonstrated gain-band- width product of 40–130 GHz and low frequency gain 45 dB. The use of InP DHBTs supports a 6.9 V differential output swing and a slew rate /52 /49/48/52V s to be achieved with as low as 40 mW dissipated power. A novel on-chip buffer circuit is used to facili