← 返回 JSSC 论文列表JSSC 2009第10期Data Converters0.13μm CMOSDelta-Sigma ADCDAC
A 01 mm 50 Wide Bandwidth Continuous-Time 61ADC Based on a Time Encoding Quantiz
该论文介绍了一种基于时间编码量化器的连续时间ADC设计，采用创新的Sigma-Delta架构，显著减小了面积并提高了能效。
ENOB 10 bits (17 MHz) / 12 bits (6.4 MHz), FoM 0.48 pJ/conversion @1.5V
模数转换器连续时间滤波器低功耗设计脉宽调制Sigma-Delta调制
▸采用时间编码量化器替代传统闪存量化器
▸利用自振荡模式实现非平坦误差频谱
▸通过sinc滤波器消除量化误差
Abstract
er , IEEE, Luis Hernandez , Member , IEEE, Susana Paton , Member , IEEE,
Andreas Wiesbauer, Member , IEEE, Richard Gaggl , Member , IEEE, and Ernesto Pun
Abstract—The ADC shown in this paper uses an innovative
Sigma-Delta /40/6/1/41architecture that replaces the flash quantizer
and mismatch corrected DAC of a multibit continuous time (CT)
modulator by a time domain encoder similar to a PWM modulator
to reduce the effective ADC area. The modulator achieves the
resolution of a multibit design using