JSSC 2009第10期Data Converters0.18μmPipeline ADC

A 25 mW 80 dB DR 36 dB SNDR 22 MSs Logarithmic Pipeline ADC Jongwoo Lee Member

一种无需复杂模拟功能的对数流水线ADC，实现高动态范围和低功耗

0.18μm CMOS, 1.62V, 22MS/s, 80dB DR, 36dB SNDR, 2.54mW

对数ADC流水线ADC动态范围低功耗CMOS

▸无需平方或其他复杂模拟功能的对数流水线ADC

▸采用1.5位每级的8位对数流水线结构

▸在0.18微米CMOS工艺下实现高动态范围和低功耗

Abstract

n Park , Member , IEEE, Jae-sun Seo, Member , IEEE, Jens Anders , Student Member , IEEE, Jorge Guilherme , Member , IEEE, and Michael P . Flynn, Senior Member , IEEE Abstract—A switched-capacitor logarithmic pipeline analog-to- digital converter (ADC) that does not require squaring or any other complex analog function is presented. This approach is attractive where a high dynamic range (DR), but not a high peak SNDR, is required. A prototype signed, 8-bit 1.5 bit-per-stage logarithmic pipeline A