JSSC 2009第11期Data Converters0.13μm CMOSDAC

A 1-GSs 6-Bit Two-Channel Two-Step ADC in 013-22m CMOS Hung-Wei Chen Student Mem

本文介绍了一种无需校准的6位1GS/s双通道两步ADC，采用0.13μm CMOS工艺实现低功耗高性能。

6-bit分辨率, 1GS/s采样率, 49mW功耗, 40.7dB SFDR, 33.8dB SNR, 33.7dB SNDR

模数转换器高速低功耗时间交织两步架构

▸采用自定时技术防止残留放大初期的干扰

▸通过增强CADC精度减少MDAC输出摆动

▸双通道两步架构实现高速低功耗

Abstract

g, and Hsin-Shu Chen , Member , IEEE Abstract—In this paper , a 6-bit 1-GS/s 49 mW two-channel two-step analog-to-digital converter (ADC) without calibra- tion is implemented in 0.13- m CMOS process. The proposed multiplying digital-to-analog converter (MDAC) processes the analog signal with two clock periods for one conversion: half for sampling, half for Coarse ADC (CADC) resolving, and one for residue ampliﬁcation. A self-timing technique is used to prevent disturbance at the beginning of the