← 返回 JSSC 论文列表JSSC 2009第11期Power Management45nm SOI
A 1255 GHz Clock Generator With High-Bandwidth Supply-Rejection Using a Regulate
45nm CMOS SOI技术实现的高带宽电源抑制时钟发生器
1.25-5GHz, 1V供电, 22dB电源抑制比, 4.5ps/100mV灵敏度
时钟发生器电源抑制CMOS相位旋转器高速互连
▸采用带复制反馈的低压差稳压器
▸通过复制负载调节实现电流源匹配
▸可编程上升/下降时间的相位旋转器
Abstract
A clock generator for high-speed chip-to-chip link re-
ceivers was implemented in a 45-nm CMOS SOI technology. A low
sensitivity to supply voltage noise was achieved by means of a low-
dropout voltage regulator using a replica feedback in the regula-
tion loop, where the replica resistance is regulated by a second loop.
We show that by adjusting the replica load the necessary matching
of the
ratio of the current sources can be achieved. A
power supply rejection of
22 dB was measured up to 1 GHz