JSSC 2009第11期RF & Wireless130nm

An 8 5 Gb/s Parallel Receiver With Collaborative Timing Recovery Ankur Agrawal, Student Member , IEEE, Andrew Liu, Pavan

设计了一种8通道、每通道5Gb/s的并行接收器，采用协作定时恢复技术，无需转发时钟。

8通道, 5Gb/s, 130nm CMOS

并行接收器定时恢复抖动跟踪CMOS相位检测器

▸协作定时恢复技术：该方法创新性地利用并行接口中传输数据流的同步性，通过多个相位检测器的错误信息协作生成全局合成时钟，显著提高了定时恢复的精度和稳定性，适用于高速数据传输场景。

▸多相位检测器错误信息合成全局时钟：该电路创新通过整合来自多个相位检测器的错误信息，生成一个全局合成时钟，有效降低了时钟抖动，提升了系统的整体性能，尤其在5 Gb/s的高速数据传输中表现优异。

▸宽带抖动跟踪：该系统创新实现了宽带抖动跟踪功能，无需增加合成时钟的抖动，显著提升了系统的抗干扰能力和信号稳定性，适用于高噪声环境下的高速数据传输。

▸130 nm CMOS测试芯片验证：通过实验验证，该技术在130 nm CMOS工艺下实现了8通道、5 Gb/s的并行接收器设计，展示了其在实际应用中的高性能和低功耗特性。

Abstract

This paper presents the design of an 8 channel, 5 Gb/s per channel parallel receiver with collaborative timing recovery and no forwarded clock. The receiver architecture exploits syn- chrony in the transmitted data streams in a parallel interface and combines error information from multiple phase detectors in the receiver to produce one global synthesized clock. This collabo- rative timing recovery scheme enables wideband jitter tracking without increasing the dithering jitter in the synthesized clock. Circuit design techniques employed to implement this receiver architecture are discussed. Experimental results from a 130 nm CMOS test chip demonstrate the enhanced tracking bandwidth and lower dithering jitter of the recovered clock.