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ROM-Based Logic RBL Design A Low-Power 16 Bit Multiplier
提出一种基于ROM的低功耗16位乘法器设计，相比传统阵列乘法器功耗降低40%。
0.18μm CMOS工艺，功耗降低40%，延迟减少44%
ROM逻辑设计低功耗乘法器进位保留加法器进位选择加法器CMOS工艺
▸采用16个4×4 ROM乘法器块
▸使用ROM实现的进位保留加法器和进位选择加法器
▸优化ROM单元消除重复行列降低功耗
Abstract
EEE, and Masaki Okajima
Abstract—We present a ROM-based 16
16 multiplier for
low-power applications. The design uses sixteen 4
4 ROM-based
multiplier blocks followed by carry-save adders and a final
carry-select adder (all ROM-based) to obtain the 32 bit output. All
ROM blocks are implemented using single transistor ROM cells
and eliminating identical rows and columns for optimizing the
power and performance. Measurement results in 0.18
m CMOS
process show a 40% reduction in power over the conv