← 返回 JSSC 论文列表JSSC 2009第12期RF & Wireless65nmEqualizer
A 10-Gbs Compact Low-Power Serial IO With DFE-IIR Equalization in 65-nm CMOS Byu
一种65nm CMOS工艺下10Gbps低功耗串行IO，采用DFE-IIR均衡技术。
10 Gb/s, 1.9 mW/Gb/s
背板通信芯片间通信紧凑型IO连续时间IIR滤波器决策反馈均衡器
▸低阻抗发射端终端：采用创新的低阻抗设计，显著降低功耗并提高信号完整性，适用于高密度硅载体互连，实测功耗效率达1.9 mW/Gb/s。
▸高阻抗接收端终端：通过高阻抗接收终端设计，有效减少信号反射和噪声干扰，提升信道适应性，支持高达27 dB的半波特损耗补偿。
▸DFE-IIR接收器设计：结合DFE和IIR滤波器的混合反馈结构，仅需单一IIR反馈抽头即可补偿多后置光标，显著降低传统多抽头DFE的面积和功耗开销。
▸紧凑型I/O架构：整体设计紧凑且高效，适用于密集硅载体互连，实测支持10 Gb/s速率，并在40毫米片上模拟硅载体信道中实现8.9 Gb/s传输。
Abstract
, Member , IEEE, Timothy O. Dickson , Member , IEEE,
John F. Bulzacchelli, Member , IEEE, and Daniel J. Friedman , Member , IEEE
Abstract—A compact and power-efficient serial I/O targeting
dense silicon carrier interconnects is reported. Based on expected
channel characteristics, the proposed I/O features low-impedance
transmitter termination, high-impedance receiver termination,
and a receiver with modified DFE with IIR filter feedback
(DFE-IIR). The DFE-IIR receiver uses a single additional IIR
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