JSSC 2009第12期Data Converters65nmDAC

A 12 bit 2.9 GS/s DAC With IM3 /60 60 dBc Beyond 1 GHz in 65 nm CMOS Chi-Hung Lin, Frank M. L. van der Goes, Jan R. Westra, Jan Mulder, Yu Lin, Erol Arslan, Emre Ayranci, Xiaodong Liu, and

65nm CMOS工艺下实现的12位2.9GS/s电流导向DAC，高频性能优异。

12bit 2.9GS/s, IM3<-60dBc@>1GHz, 188mW功耗

CMOS电流导向数模转换器高频高速

▸采用局部共源共栅结构提升高频性能

▸“always-ON”偏置技术优化开关特性

▸在1GHz以上实现IM3优于60dBc

Abstract

an Mulder, Yu Lin, Erol Arslan, Emre Ayranci, Xiaodong Liu, and Klaas Bult Abstract—A 12 bit 2.9 GS/s current-steering DAC implemented in 65 nm CMOS is presented, with an /51 /54/48dBc be- yond 1 GHz while driving a 50 /10load with an output swing of 2.5 /112/112/100and dissipating a power of 188 mW. The SFDR measured at 2.9 GS/s is better than 60 dB beyond 340 MHz while the SFDR measured at 1.6 GS/s is better than 60 dB beyond 440 MHz. The in- crease in performance at high-frequencies, compa