JSSC 2009第12期Data Converters90nmPipeline ADCDAC

A 130 mW 100 MSs Pipelined ADC With 69 dB SNDR Enabled by Digital Harmonic Disto

提出一种采用数字谐波失真校正技术的130mW 100MS/s流水线ADC，实现69dB SNDR。

90nm CMOS, 1.2V/1.0V, 100MS/s, 70dB SNR, 85dB SFDR

流水线ADC数字校准谐波失真DAC噪声消除低功耗

▸数字谐波失真校正(HDC)：首次在集成电路中实现数字背景谐波失真校正技术，通过补偿残余放大器增益误差和非线性，显著提升ADC的线性度，使SFDR达到85 dB。

▸DAC噪声消除(DNC)：采用数字背景校准技术消除DAC电容失配噪声，结合HDC技术实现低电压操作，功耗降至130 mW，较同类先进流水线ADC显著降低。

▸低电压操作创新：通过HDC和DNC协同优化，在1.2V/1.0V模拟/数字电源下实现100 MS/s采样率，突破传统设计对高压供电的依赖，兼顾70 dB SNR与高能效。

▸系统级能效优化：在90 nm CMOS工艺中集成双校准技术，以49dBFS动态范围达成69 dB SNDR，为高速高精度ADC提供可扩展的低功耗架构范例。

Abstract

This paper presents a pipelined ADC with two fully integrated digital background calibration techniques: harmonic distortion correction (HDC) to compensate for residue ampliﬁer gain error and nonlinearity and DAC noise cancellation (DNC) to compensate for DAC capacitor mismatches. It is the ﬁrst IC implementation of HDC, and the results demonstrate that HDC and DNC together facilitate low-voltage operation and enable re- ductions in power dissipation relative to comparable conventional state-of-