JSSC 2009第12期Data Converters0.18μmPipeline ADCNeural Network Accelerator

A 16-bit, 125 MS/s, 385 mW, 78.7 dB SNR CMOS Pipeline ADC Siddharth Devarajan

一款16位125MS/s低功耗流水线ADC，采用0.18μm CMOS工艺，具有数字校准和抖动功能。

16-bit, 125MS/s, 385mW, 78.7dB SNR, 1.8V

ADC流水线CMOS数字校准抖动

▸SHA-less 4-bit前端设计降低功耗

▸工厂数字校准校正电容失配

▸可选抖动功能改善小信号线性度

Abstract

Decker, Abhishek Kamath, and Paul Wilkins Abstract—A 16-bit 125 MS/s pipeline analog-to-digital converter (ADC) implemented in a 0.18 m CMOS process is presented in this paper. A SHA-less 4-bit front-end is used to achieve low power and minimize the size of the input sampling capacitance in order to ease drivability. The ADC includes foreground factory digital calibration to correct for capacitor mismatches and dithering that can be optionally enabled to improve small-signal linearity. This AD