JSSC 2009第12期Data Converters

A 18 V 10 GSs 10b Self-Calibrating Uniﬁed-Folding-Interpolating ADC With 91 ENOB

提出一种新型统一折叠插值ADC架构，通过递归使用前一折叠级作为后续级的粗通道，简化高分辨率扩展。

10-bit, 1.8V, 1 GS/s, 9.1 ENOB at Nyquist

折叠插值ADC统一折叠架构递归设计高分辨率低功耗

▸创新点1：统一折叠架构（Unified-Folding Architecture）通过将传统并行粗通道替换为递归折叠级联结构，消除了粗/细通道间的匹配问题，实现了10位分辨率下仅需六级折叠级联（总折叠阶数729），显著降低了系统复杂度。

▸创新点2：递归粗通道复用技术（Recursive Coarse Channel Reuse）利用前一级折叠输出直接作为下一级的粗通道参考，避免了独立粗量化模块的功耗与面积开销，在1.8V电源下实现1.2W/channel的低功耗表现。

▸创新点3：高精度自校准技术（Self-Calibrating Mechanism）通过动态校正折叠级间的增益误差与偏移，在1GS/s采样率下达成DNL≤0.48LSB/INL≤0.53LSB，Nyquist输入时仍保持9.1 ENOB的高线性度。

▸创新点4：折叠-插值混合结构（Folding-Interpolating Hybrid）结合折叠级的高频优势与插值器的低功耗特性，在1GHz输入频率时实现8.8 ENOB，创下当前折叠架构ADC的最高频宽纪录。

Abstract

An advance in folding-interpolating analog-to-digital converters (ADCs) is demonstrated which simpliﬁes their exten- sion to higher resolution by building the converter out of iden- tical but scaled pipelined cascaded folding stages. In this uniﬁed folding architecture the parallel coarse channel has been elimi- nated by recursively using the previous folding stage as the coarse channel for each following cascaded stage. This new architecture is demonstrated in a 10-bit ADC using six cascaded fo