← 返回 JSSC 论文列表JSSC 2009第12期Data Converters0.18 μm CMOSDACPLL
A 1 MHz Bandwidth 6 GHz 018 22m CMOS Type-I 16Fractional-N Synthesizer for WiMAX
一款6 GHz Type-I分数分频PLL,采用噪声消除DAC和离散时间采样保持环路滤波器,带宽1 MHz。
6 GHz, 1 MHz带宽, 0.01 ppm精度, 60 MHz频率步进, 11 μs锁定时间, 102 dBc/Hz@300 kHz, 130 dBc/Hz@3 MHz
分数分频合成器锁相环量化噪声Sigma-Delta调制器宽带
▸噪声消除电荷泵DAC电路:采用创新的噪声消除技术,通过DAC电路有效降低量化噪声超过25 dB,显著提升系统信噪比,属于电路级创新。
▸固有线性PFD(相位频率检测器):设计了一种具有固有线性特性的PFD,避免了传统PFD的非线性问题,提高了相位检测的精度和稳定性,属于方法创新。
▸离散时间采样保持环路滤波器:引入离散时间采样保持技术,优化了环路滤波器的性能,使其在1 MHz带宽下仍能保持低噪声和高稳定性,属于系统级创新。
▸高集成度与低功耗设计:在0.18微米CMOS工艺下实现6 GHz频率合成器,仅消耗26 mA电流,展示了高性能与低功耗的完美结合,属于工艺与设计协同创新。
Abstract
E, Waleed Khalil , Member , IEEE, and Bertan Bakkaloglu , Senior Member , IEEE
Abstract—A 6 GHz Type-I fractional-
PLL with noise-can-
celling DAC and discrete-time sample and hold loop-filter is
presented. The 1 MHz bandwidth PLL utilizes an inherently
linear PFD and noise-cancelling charge-pump DAC circuit to
reduce quantization noise by more than 25 dB. The worst case
near-integer in-band spur is measured at
61 dBc and the inte-
grated RMS phase error is
42 dBc. The measured in-band phase
no