← 返回 JSSC 论文列表JSSC 2009第12期Clocking & PLLs
A 2.0 Gb/s Clock-Embedded Interface for Full-HD 10-Bit 120 Hz LCD Drivers With 1/5-Rate Noise-Tolerant Phase and Frequency Recovery Koichi Y amaguchi, Y oshihiko Hori, Keiichi Nakajima
开发了一种2.0 Gb/s时钟嵌入式接口Advanced-PPmL™，用于LCD驱动器的高速数据传输和传输介质面积减小。
3.0 V电源下CDR功耗93 mW，恢复时钟的rms抖动为11 ps（PRBS7模式）
时钟嵌入式接口LCD驱动器高速数据传输功耗优化抗噪声时钟恢复
▸1/5速率相位频率检测器降低25%功耗
▸相位控制信号的脉冲滤波
▸基于4B5B的接口协议实现抗噪声时钟恢复
Abstract
A 2.0 Gb/s clock-embedded interface for LCD drivers, Advanced-PPmL™, has been developed for high-speed data transfer and reduced area in transmission media. Only one pair of differential signals is needed to control the LCD driver and to display images. A newly developed 1/5-rate phase frequency detector helps achieve a 25% power reduction compared with a half-rate architecture. Pulse filtering of phase control signals and a 4B5B-based interface protocol have been developed for noise-tolerant clock recovery. Power consumption in the clock and data recovery (CDR) is 93 mW with a 3.0 V supply. The rms jitter in the recovered clock is 11 ps when a PRBS7 pattern is used.