Abstract
Kaeriyama, Member , IEEE, Yasushi Amamiya, Hidemi Noguchi, Zin Yamazaki,
Tomoyuki Yamase, Member , IEEE, Kenichi Hosoya , Member , IEEE, Minoru Okamoto, Shiro Tomari,
Hiroshi Yamaguchi, Hiroaki Shoda, Hironobu Ikeda, Shinji Tanaka, Tsugio Takahashi, Risato Ohhira,
Arihide Noda, Ken’ichiro Hijioka, Akira Tanabe, Sadao Fujita, and Nobuhiro Kawahara
Abstract—A fully integrated 40 Gb/s transmitter and receiver
chipset with SFI-5 interface is implemented in a 65 nm CMOS tech-
nology and mounted in a