← 返回 JSSC 论文列表JSSC 2009第12期Clocking & PLLs0.18μmPLLVCO
A Low Noise Sub-Sampling PLL in Which Divider Noise is Eliminated and PDCP Noise
一种低噪声子采样PLL，消除分频器噪声并降低PDCP噪声
0.18μm CMOS, 1.8V, 4.2mA, 2.2GHz, 0.15ps rms jitter
低抖动子采样锁相环相位噪声频率合成器
▸采用子采样相位检测器/电荷泵(PD/CP)降低噪声
▸锁定状态下无需分频器，消除分频器噪声和功耗
▸附加频率锁定环路确保频率锁定且不恶化抖动性能
Abstract
nt Member , IEEE , Eric A. M. Klumperink , Senior Member , IEEE ,
Mounir Bohsali, Student Member , IEEE, and Bram Nauta , Fellow, IEEE
Abstract—This paper presents a 2.2-GHz low jitter sub-sam-
pling based PLL. It uses a phase-detector/charge-pump (PD/CP)
that sub-samples the VCO output with the reference clock. In
contrast to what happens in a classical PLL, the PD/CP noise is
not multiplied by
/50in this sub-sampling PLL, resulting in a
low noise contribution from the PD/CP. Moreover, no frequ