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A Piecewise Linear 10 Bit DAC Architecture With Drain Current Modulation for Com
提出一种用于LCD数据驱动的分段线性10位DAC，采用漏极电流调制插值法，提升非线性液晶特性下的有效分辨率。
DNL 0.37 LSB，最大输出电压偏差均值6.35 mV，标准差0.54 mV，芯片面积缩减8.2%
分段线性DAC漏极电流调制插值LCD数据驱动
▸创新点1：分段线性10位DAC架构，通过将DAC的输出特性分段线性化，有效提高了在非线性液晶特性下的有效比特分辨率，优于传统的线性10位开关电容DAC。
▸创新点2：漏极电流调制插值法，采用创新的插值技术，通过调制漏极电流来实现更精确的电压输出，显著改善了DAC的微分非线性（DNL）至0.37 LSB。
▸创新点3：同时设计流程优化失配和非线性效应，通过基于失配和非线性效应估计的同步设计流程，实现了优异的通道均匀性，最大输出电压偏差的均值和标准差分别为6.35 mV和0.54 mV。
▸创新点4：芯片面积缩减，新型插值方法使数据驱动器的芯片面积比传统的8位R-DAC数据驱动器减少了8.2%，提高了集成度和成本效益。
Abstract
Member , IEEE, Hyung-Min Lee, Sung-Woo Lee, Gyu-Hyeong Cho , Member , IEEE,
Hyoung Rae Kim, Y oon-Kyung Choi, and Myunghee Lee
Abstract—A piecewise linear 10 bit DAC for LCD data driver
with robust interpolation method of drain current modulation is
presented. It has higher effective bit resolution than the linear
10 bit switched-capacitor DAC when applied to nonlinear liquid
crystal characteristics. By adopting a simultaneous design flow
based on the estimations for the mismatch and nonlinearity