← 返回 JSSC 论文列表JSSC 2009第12期Other65nm
An Embedded 65 nm CMOS Baseband IQ 48 MHz–1 GHz Dual Tuner for DOCSIS 3.0 Francesco Gatta, Ray Gomez, Young J. Shin, Takayuki Hayashi, Hanli Zou, James Y . C. Chang, Leonard Dauphinee, Jianhong Xiao , Student Member , IEEE, Dave S.-H. Chang, Tai-Hong Chih, Massimo Brandolini
65nm CMOS嵌入式双调谐器，支持DOCSIS 3.0，无需外部组件或SAW滤波器。
65nm CMOS, 48-1004MHz带宽, 320Mb/s(Annex B), 400Mb/s(Annex A)
DOCSIS 3.0CMOS调谐器嵌入式系统数字镜像抑制谐波抑制
▸创新点1：谐波抑制前端 - 该方法创新通过优化前端电路设计，有效抑制了谐波干扰，提升了信号接收的纯净度，无需外部组件或SAW滤波器即可满足SCTE 40标准。
▸创新点2：低噪声高分辨率PLL - 该电路创新采用低噪声设计和高频率分辨率技术，显著降低了相位噪声，提高了频率合成的精度，支持48 MHz至1 GHz的宽带调谐。
▸创新点3：数字镜像抑制 - 该系统创新利用数字信号处理技术，实现了高效的镜像信号抑制，提升了多通道接收的性能，支持DOCSIS 3.0和机顶盒应用。
▸创新点4：嵌入式65 nm CMOS技术 - 该工艺创新首次在65 nm纯数字CMOS技术中实现了多通道宽带调谐器的集成，显著降低了功耗和成本，提升了系统的集成度和性能。
Abstract
An embedded CMOS digital dual tuner for DOCSIS 3.0 and set-top box applications is presented. The dual tuner down-converts a total of ten 6 MHz Annex B channels or eight 8 MHz Annex A channels, for a maximum data rate of 320 Mb/s in Annex B and 400 Mb/s in Annex A mode. The dual tuner exceeds all the stringent SCTE 40 specifications over the 48–1004 MHz bandwidth, without using any external components or SA W fil- ters. Enabling technologies are a harmonic rejection front-end, a low-noise high-frequency resolution phase-locked loop (PLL) and digital image rejection. To our knowledge this is the first reported multi-channel Broadband Tuner embedded in a DOCSIS 3.0 System on a Chip implemented in a 65 nm pure digital CMOS technology.