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Digitally Enhanced Software-Defined Radio Receiver Robust to Out-of-Band Interference
提出一种抗带外干扰的软件定义无线电接收器,采用数字增强技术提高鲁棒性。
34 dB增益,4 dB噪声系数,带外IIP3达54dBm,工作频率达6 GHz
软件定义无线电带外干扰谐波抑制自适应干扰消除多相时钟
▸模拟两级多相谐波抑制技术:通过创新的两级多相结构实现超过60 dB的谐波抑制,显著提升接收机对带外干扰的鲁棒性,解决了传统单级结构在失配条件下的性能下降问题。
▸数字自适应干扰消除技术:采用数字信号处理算法动态抑制主导谐波干扰,实现至少80 dB的干扰消除能力,大幅提升复杂电磁环境下的接收机线性度和灵敏度。
▸高精度多相时钟生成器:专为谐波抑制设计的时钟系统,支持8相位LO信号生成,工作频率可达0.9 GHz(主时钟7.2 GHz),通过精密时序控制确保多相处理链路的失配容限。
▸混合增益分配架构:突破性地将射频增益转移至基带处理,结合低通滤波抑制带外阻塞,实现带外IIP3达54 dBm的高线性度,同时优化系统噪声系数至4 dB。
Abstract
A software-defined radio (SDR) receiver with im- proved robustness to out-of-band interference (OBI) is presented. Two main challenges are identified for an OBI-robust SDR re- ceiver: out-of-band nonlinearity and harmonic mixing. V oltage gain at RF is avoided, and instead realized at baseband in com- bination with low-pass filtering to mitigate blockers and improve out-of-band IIP3. Two alternative “iterative” harmonic-rejec- tion (HR) techniques are presented to achieve high HR robust to mismatch: a) an analog two-stage polyphase HR concept, which enhances the HR to more than 60 dB; b) a digital adaptive interference cancelling (AIC) technique, which can suppress one dominating harmonic by at least 80 dB. An accurate multi- phase clock generator is presented for a mismatch-robust HR. A proof-of-concept receiver is implemented in 65 nm CMOS. Measurements show 34 dB gain, 4 dB NF , and /43/51 /53dBm in-band IIP3 while the out-of-band IIP3 is /43/49/54dBm without fine tuning. The measured RF bandwidth is up to 6 GHz and the 8-phase LO works up to 0.9 GHz (master clock up to 7.2 GHz). At 0.8 GHz LO, the analog two-stage polyphase HR achieves a second to sixth order /54/48dB over 40 chips, while the digital AIC technique achieves /56/48dB for the dominating harmonic. The total power consumption is 50 mA from a 1.2 V supply.