Abstract
im, Soon-Hong Ahn,
Soo-Ho Cha, Jaesung Ahn, DukMin Kwon, Jae-Wook Lee, Han-Sung Joo, Woo-Seop Kim , Member , IEEE,
Dong Hyeon Jang, Nam Seog Kim, Jung-Hwan Choi, Tae-Gyeong Chung, Jei-Hwan Y oo, Joo Sun Choi,
Changhyun Kim, Senior Member , IEEE, and Y oung-Hyun Jun
Abstract—An 8 Gb 4-stack 3-D DDR3 DRAM with
through-Si-via is presented which overcomes the limits of
conventional modules. A master-slave architecture is proposed
which decreases the standby and active power by 50 and 25%,
respective