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JSSC 2010第1期Wireline I/O75nmDRAM

A 75 nm 7 Gb/s/pin 1 Gb GDDR5 Graphics Memory Device With Bandwidth Improvement Techniques Rex Kho, David Boursin, Martin Brox

本文介绍了一种75nm工艺的7 Gb/s/pin 1 Gb GDDR5图形内存设备,通过多种电路设计优化技术提升带宽。
7 Gb/s/pin, 1 Gb GDDR5, 75nm DRAM
GDDR5带宽提升电路设计75nm工艺图形内存
快速列访问的阵列架构
利用GDDR5接口特殊训练/跟踪需求的命令FIFO
提升读取眼图高度的增强型发射器
Abstract
eter Gregorius , Member , IEEE, Heinz Hoenigschmid , Member , IEEE, Bianka Kho, Sabine Kieser, Daniel Kehrer, Maksim Kuzmenka, Udo Moeller, Pavel Veselinov Petkov, Manfred Plan, Michael Richter, Ian Russell, Kai Schiller, Ronny Schneider, Kartik Swaminathan, Bradley Weber, Julien Weber, Ingo Bormann, Fabien Funfrock, Mario Gjukic, Wolfgang Spirkl, Holger Steffens, Jörg Weller, Member , IEEE, and Thomas Hein Abstract—Modern graphics subsystems (gaming PCs, mid- high end graphics cards, game conso