← 返回 JSSC 论文列表JSSC 2010第2期RF & Wireless0.13微米Equalizer
A Merged CMOS Digital Near-End Crosstalk Canceller and Analog Equalizer for Mult
0.13微米CMOS工艺实现数字近端串扰消除与模拟均衡器合并设计，支持5Gb/s数据传输。
5 Gb/s, BER 10^-12, 49.7 ps抖动, 177 mW功耗
近端串扰消除模拟均衡器CMOS多通道串行链路SSB-LMS
▸创新点1：数字近端串扰消除器与模拟均衡器合并设计，通过集成数字NEXT消除和模拟均衡功能，显著提升了多通道串行链路接收器的信号完整性，支持5 Gb/s数据传输速率，并有效克服了10英寸和20英寸FR4迹线的信道损耗和串扰问题。
▸创新点2：采用SSB-LMS（符号-符号块最小均方）电路，优化了自适应均衡过程，提高了收敛速度和稳定性，实测误码率（BER）低至10^-12，峰峰值抖动仅为49.7 ps，展现了卓越的信号恢复能力。
▸创新点3：多通道串行链路接收器优化，通过创新的电路设计和布局技术，在0.13微米CMOS工艺下实现了0.56 mm²的紧凑面积，同时整体功耗控制在177 mW（1.2 V供电），兼顾了高性能与低功耗需求。
▸创新点4：针对高密度PCB布局的优化，通过5-mil线宽和7-mil间距的FR4迹线设计，验证了方案在复杂电磁环境下的鲁棒性，为高速互连系统提供了可扩展的解决方案。
Abstract
A digital near-end crosstalk (NEXT) canceller
merged with an analog equalizer for multi-lane serial-link
receivers has been realized in 0.13
m CMOS technology. By ap-
plying the proposed sign-sign block least-mean-square (SSB-LMS)
circuit, a 5 Gb/s pseudorandom binary sequence (PRBS) of 2
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1
suffered from both the channel loss and NEXT over 10- and
20-inch FR4 traces with the width of 5-mil and the spacing of
7-mil is successfully equalized. The measured bit error rate (BER)
is 10
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