← 返回 JSSC 论文列表JSSC 2010第2期Power Management0.13μmPLL
A PVT Tolerant 10 to 500 MHz All-Digital Phase-Locked Loop With Coupled TDC and
提出一种全数字锁相环(ADPLL)，采用时间间隔信号处理，具有PVT稳定性。
0.13μm CMOS, 0.6-1.6V, 10-500MHz
全数字锁相环时间数字转换器数字控制振荡器自由运行环形振荡器PVT稳定性
▸采用自由运行环形振荡器(FRO)提供TDC和DCO的共同时钟分辨率
▸数字分频器在频率倍增因子变化时保持环路增益恒定
▸全数字架构实现工艺、电压、温度(PVT)变化下的稳定工作
Abstract
Lin, Shengdong Zhang, and Y angyuan Wang
Abstract—An all-digital phase-locked loop (ADPLL) with
all components working with time interval or period signals is
demonstrated. The ADPLL consists mainly of a free-running ring
oscillator (FRO), a time to digital converter (TDC), a digitally con-
trolled oscillator (DCO), a digital divider and a digital loop filter.
In the proposed architecture, the TDC and DCO have an equal
time resolution from the common FRO. The digital divider keeps
the loop gain