← 返回 JSSC 论文列表JSSC 2010第2期Power Management0.35μmLDO
An Output-Capacitorless Low-Dropout Regulator With Direct V oltage-Spike Detecti
提出一种无输出电容的低压差稳压器，采用直接电压尖峰检测电路提升瞬态响应。
0.35μm CMOS, 1V供电, 0.8V输出, 200mV压差, 66.7mA最大输出电流
电容耦合低压差稳压器电压尖峰瞬态响应无输出电容
▸创新点1：基于电容耦合的电压尖峰检测电路（电路创新）。该电路利用LDO输出端的快速瞬态电压，通过电容耦合机制检测电压尖峰，从而瞬时增加偏置电流，显著提升瞬态响应。
▸创新点2：瞬态响应显著提升（性能创新）。通过改进功率晶体管栅极的转换速率，LDO的电压尖峰和恢复时间分别降至70mV和3μs，相比未使用检测电路的420mV和30μs有显著改善。
▸创新点3：低功耗设计（系统创新）。该LDO在标准0.35μm CMOS技术下实现，功耗仅为19μA，适用于低功耗应用场景。
▸创新点4：无输出电容设计（系统创新）。该LDO无需外部输出电容，简化了系统设计并降低了成本，同时保持了高性能的电压调节能力。
Abstract
r , IEEE
Abstract—An output-capacitorless low-dropout regulator
(LDO) with a direct voltage-spike detection circuit is presented
in this paper. The proposed voltage-spike detection is based on
capacitive coupling. The detection circuit makes use of the rapid
transient voltage at the LDO output to increase the bias current
momentarily. Hence, the transient response of the LDO is signif-
icantly enhanced due to the improvement of the slew rate at the
gate of the power transistor.
The proposed volt