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Comments and Corrections Correction on A 5-Gbspin Transceiver for DDR Memory Int
论文作者对未引用前人工作表示道歉，并承认其5Gb/s/pin收发器的串扰抑制方案灵感来源于前人研究。
5Gb/s/pin
收发器串扰抑制相位补偿幅度补偿DDR内存
▸创新点1：5Gb/s/pin收发器设计，采用高速数据传输技术，显著提升了DDR内存接口的数据传输速率，支持高达5Gb/s的传输速率，适用于高性能计算和大容量存储应用。
▸创新点2：串扰抑制方案，通过创新的电路设计和信号处理技术，有效降低了高速数据传输中的串扰问题，提升了信号完整性和系统稳定性。
▸创新点3：相位和幅度补偿方法，采用两步骤补偿策略，优化了信号传输的相位和幅度，进一步提高了数据传输的准确性和可靠性。
▸创新点4：基于[2]的改进型“glitch canceller”电路，在幅度补偿中采用了改进设计，显著减少了信号中的毛刺现象，提升了整体系统性能。
Abstract
Kwang-Il Oh, Lee-Sup Kim, Kwang-Il Park, Y oung-Hyun Jun,
Joo Sun Choi, and Kinam Kim
In the above paper [1], we had failed to acknowledge the idea and
work of the author of [2] when the work done in [1] is a direct reflec-
tion of the work done in [2]. We give a sincere apology for crediting the
ideas on the paper as our own. [1] presents a 5 Gb/s/pin transceiver with
a crosstalk suppression scheme. The scheme provides crosstalk com-
Manuscript received October 27, 2009. Current version publishe