A 002-mm509-Bit 50-MSs Cyclic ADC in 90-nm Digital CMOS Technology Y en-Chuan Hu

Abstract

DC employs a track-and-evaluation technique for enhancing the speed of residue evaluation. The pro- posed multiply-by-two circuit has a shorter evaluation time than the conventional design due to the application of a partial positive feedback topology. The residue evaluation and sampling phases are merged to reduce the conversion latency. Hence, only four clock cycles are required to perform the 9-bit conversion. The proposed 0.02-mm /50ADC has been fabricated in 90-nm digital CMOS tech- nology.