All-Digital Circuits for Measurement of Spatial V ariation in Digital Circuits

Abstract

Increased variation in CMOS processes due to scaling results in greater reliance on accurate variation models in developing circuit methods to mitigate variation. This paper inves- tigates spatial variation in digital circuit performance: we describe a test-chip in 90 nm CMOS containing all-digital measurement circuits capable of extracting accurate variation data. Specifically, we use replicated 64-bit Kogge–Stone adders, ring oscillators (ROs) of varying gate type and stage length and an all-di