← 返回 JSSC 论文列表JSSC 2010第3期Digital Circuits65nm
An Ultra-Low-Energy Multi-Standard JPEG Co-Processor in 65 nm CMOS With SubNear
65nm CMOS工艺下实现超低能耗的多标准JPEG协处理器设计
0.4V供电电压下每周期0.75pJ能耗，2.5MHz频率
超低能耗亚阈值操作JPEG协处理器65nm CMOS并行架构
▸架构级并行性以补偿吞吐量下降
▸可配置平衡器缓解nMOS和pMOS晶体管在亚阈值/近阈值操作中的不匹配
▸指状结构并行晶体管利用不匹配提高电流驱动能力
Abstract
ose Pineda de Gyvez , Fellow, IEEE, Henk Corporaal , Member , IEEE, and
Yajun Ha, Senior Member , IEEE
Abstract—We present a design technique for (near) subthreshold
operation that achieves ultra low energy dissipation at through-
puts of up to 100 MB/s suitable for digital consumer electronic ap-
plications. Our approach employs i) architecture-level parallelism
to compensate throughput degradation, ii) a configurable
/84bal-
ancer to mitigate the
/84mismatch of nMOS and pMOS transis-
tors oper