Abstract
EE, Y asuyuki Okuma, Kiichi Niitsu , Member , IEEE,
Y asuhisa Shimazaki, Member , IEEE, Y asufumi Sugimori, Y oshinori Kohama, Kazutaka Kasuga, Itaru Nonomura,
Naohiko Irie, Toshihiro Hattori , Member , IEEE, Atsushi Hasegawa, and Tadahiro Kuroda , Fellow, IEEE
Abstract—This paper describes a three-dimensional (3-D)
system integration of a full-fledged processor chip and two
memory chips using inductive coupling. To attain a 3-D commu-
nication link with a smaller area and lower power-consumption